stm32 /stm32n6 /STM32N647 /HPDMA /HPDMA_C7CIDCFGR

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Interpret as HPDMA_C7CIDCFGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)CFEN 0 (B_0x0)SEM_EN 0 (B_0x0)SCID0 (B_0x0)SEM_WLIST_CID0 0 (B_0x0)SEM_WLIST_CID1 0 (B_0x0)SEM_WLIST_CID2 0 (B_0x0)SEM_WLIST_CID3 0 (B_0x0)SEM_WLIST_CID4 0 (B_0x0)SEM_WLIST_CID5 0 (B_0x0)SEM_WLIST_CID6

SEM_WLIST_CID0=B_0x0, SCID=B_0x0, SEM_WLIST_CID3=B_0x0, SEM_WLIST_CID2=B_0x0, SEM_WLIST_CID6=B_0x0, SEM_EN=B_0x0, CFEN=B_0x0, SEM_WLIST_CID4=B_0x0, SEM_WLIST_CID5=B_0x0, SEM_WLIST_CID1=B_0x0

Description

HPDMA channel 7 CID register

Fields

CFEN

CID filtering enable of the channel x

0 (B_0x0): CID filtering disabled for when accessing a channel x register/field

1 (B_0x1): CID filtering enabled for when accessing a channel x register/field

SEM_EN

semaphore mode enable (for the CID allocation policy to the channel x)

0 (B_0x0): semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0].

1 (B_0x1): semaphore mode enabled. CID allocation policy to the channel x is defined by the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX.

SCID

allocate a static/single CID to the channel x (for when the channel x CID configuration is not in semaphore mode)

0 (B_0x0): CID0 allocated to the channel x

1 (B_0x1): CID1 allocated to the channel x

2 (B_0x2): CID2 allocated to the channel x

3 (B_0x3): CID3 allocated to the channel x

4 (B_0x4): CID4 allocated to the channel x

5 (B_0x5): CID5 allocated to the channel x

6 (B_0x6): CID6 allocated to the channel x

SEM_WLIST_CID0

white-listed CID0 in the CID allocation pool (for when the channel x in semaphore mode)

0 (B_0x0): CID0 black-listed in the semaphore-based CID allocation pool

1 (B_0x1): CID0 white-listed in the semaphore-based CID allocation pool

SEM_WLIST_CID1

white-listed CID1 in the CID allocation pool (for when the channel x in semaphore mode)

0 (B_0x0): CID1 black-listed in the semaphore-based CID allocation pool

1 (B_0x1): CID1 white-listed in the semaphore-based CID allocation pool

SEM_WLIST_CID2

white-listed CID2 in the CID allocation pool (for when the channel x in semaphore mode)

0 (B_0x0): CID2 black-listed in the semaphore-based CID allocation pool

1 (B_0x1): CID2 white-listed in the semaphore-based CID allocation pool

SEM_WLIST_CID3

white-listed CID3 in the CID allocation pool (for when the channel x in semaphore mode)

0 (B_0x0): CID3 black-listed in the semaphore-based CID allocation pool

1 (B_0x1): CID3 white-listed in the semaphore-based CID allocation pool

SEM_WLIST_CID4

white-listed CID4 in the CID allocation pool (for when the channel x in semaphore mode)

0 (B_0x0): CID4 black-listed in the semaphore-based CID allocation pool

1 (B_0x1): CID4 white-listed in the semaphore-based CID allocation pool

SEM_WLIST_CID5

white-listed CID5 in the CID allocation pool (for when the channel x in semaphore mode)

0 (B_0x0): CID5 black-listed in the semaphore-based CID allocation pool

1 (B_0x1): CID5 white-listed in the semaphore-based CID allocation pool

SEM_WLIST_CID6

white-listed CID6 in the CID allocation pool (for when the channel x in semaphore mode)

0 (B_0x0): CID6 black-listed in the semaphore-based CID allocation pool

1 (B_0x1): CID6 white-listed in the semaphore-based CID allocation pool

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