stm32 /stm32n6 /STM32N647 /I3C1 /I3C_BCR

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Interpret as I3C_BCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)BCR0 0 (B_0x0)BCR2 0 (B_0x0)BCR6

BCR2=B_0x0, BCR0=B_0x0, BCR6=B_0x0

Description

I3C bus characteristics register

Fields

BCR0

max data speed limitation

0 (B_0x0): no limitation

1 (B_0x1): limitation, as described by I3C_GETMXDSR.

BCR2

in-band interrupt (IBI) payload

0 (B_0x0): no data byte follows the accepted IBI

1 (B_0x1): at least one mandatory data byte follows the accepted IBI (and at most 4 data bytes)

BCR6

Controller capable

0 (B_0x0): I3C target (no controller capable)

1 (B_0x1): I3C controller capable

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