IBIACK=B_0x0, IBIDEN=B_0x0, DIS=B_0x0, CRACK=B_0x0, SUSP=B_0x0
I3C device 1 characteristics register
| DA | Assigned I3C dynamic address to target x (when the I3C acts as controller) |
| IBIACK | IBI request acknowledge (when the I3C acts as controller) 0 (B_0x0): an IBI request from target x must be NACK-ed 1 (B_0x1): an IBI request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed |
| CRACK | Controller-role request acknowledge (when the I3C acts as controller) 0 (B_0x0): a controller-role request from target x must be NACK-ed 1 (B_0x1): a controller-role request (with 7-bit dynamic address DA[6:0]) from target x must be ACKed |
| IBIDEN | IBI data enable (when the I3C acts as controller) 0 (B_0x0): no data byte follows the acknowledged IBI from target x 1 (B_0x1): the mandatory data byte MDB[7:0] follows the acknowledged IBI from target x |
| SUSP | Suspend/stop I3C transfer on received IBI (when the I3C acts as controller) 0 (B_0x0): C-FIFO and TX-FIFO are not flushed after an IBI request from target x is acknowledged and completed, and depending on the presence or absence of a next control word, a repeated start or a stop is emitted 1 (B_0x1): I3C transfer is stopped and both C-FIFO and TX-FIFO are flushed after receiving an IBI request from target x |
| DIS | DA[6:0] write disabled (when the I3C acts as controller) 0 (B_0x0): write to DA[7:0] and to IBIDEN in the I3C_DEVRx register is allowed 1 (B_0x1): write to DA[7:0] and to IBIDEN is disabled/locked |