OFNEIE=B_0x0, IFNFIE=B_0x0, JCEN=B_0x0, IDMAEN=B_0x0, OFF=B_0x0, IFF=B_0x0, EOCIE=B_0x0, OFTIE=B_0x0, ODMAEN=B_0x0, HPDIE=B_0x0, IFTIE=B_0x0
JPEG control register
| JCEN | JPEG core enable 0 (B_0x0): Disabled (internal registers are reset). 1 (B_0x1): Enabled (internal registers are accessible). |
| IFTIE | Input FIFO threshold interrupt enable 0 (B_0x0): Disabled 1 (B_0x1): Enabled |
| IFNFIE | Input FIFO not full interrupt enable 0 (B_0x0): Disabled 1 (B_0x1): Enabled |
| OFTIE | Output FIFO threshold interrupt enable 0 (B_0x0): Disabled 1 (B_0x1): Enabled |
| OFNEIE | Output FIFO not empty interrupt enable 0 (B_0x0): Disabled 1 (B_0x1): Enabled |
| EOCIE | End of conversion interrupt enable 0 (B_0x0): Disabled 1 (B_0x1): Enabled |
| HPDIE | Header parsing done interrupt enable 0 (B_0x0): Disabled 1 (B_0x1): Enabled |
| IDMAEN | Input DMA enable 0 (B_0x0): Disabled 1 (B_0x1): Enabled |
| ODMAEN | Output DMA enable 0 (B_0x0): Disabled 1 (B_0x1): Enabled |
| IFF | Input FIFO flush 0 (B_0x0): No effect 1 (B_0x1): Input FIFO is flushed |
| OFF | Output FIFO flush 0 (B_0x0): No effect 1 (B_0x1): Output FIFO is flushed |