LPTIM1_CFGR2

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Interpret as LPTIM1_CFGR2

IC2SEL=B_0x0, IC1SEL=B_0x0, IN1SEL=B_0x0, IN2SEL=B_0x0

LPTIM1 configuration register 2

IN1SEL	LPTIM input 1 selection 0 (B_0x0): lptim_in1_mux0 1 (B_0x1): lptim_in1_mux1 2 (B_0x2): lptim_in1_mux2 3 (B_0x3): lptim_in1_mux3
IN2SEL	LPTIM input 2 selection 0 (B_0x0): lptim_in2_mux0 1 (B_0x1): lptim_in2_mux1 2 (B_0x2): lptim_in2_mux2 3 (B_0x3): lptim_in2_mux3
IC1SEL	LPTIM input capture 1 selection 0 (B_0x0): lptim_ic1_mux0 1 (B_0x1): lptim_ic1_mux1 2 (B_0x2): lptim_ic1_mux2 3 (B_0x3): lptim_ic1_mux3
IC2SEL	LPTIM input capture 2 selection 0 (B_0x0): lptim_ic2_mux0 1 (B_0x1): lptim_ic2_mux1 2 (B_0x2): lptim_ic2_mux2 3 (B_0x3): lptim_ic2_mux3

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