Regviz

stm32 /stm32n6 /STM32N647 /LPTIM1 /LPTIM1_ISR_OUTPUT

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as LPTIM1_ISR_OUTPUT

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32n6/STM32N645/LPTIM1/LPTIM1_ISR_OUTPUT#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)CC1IF 0 (ARRM)ARRM 0 (EXTTRIG)EXTTRIG 0 (CMP1OK)CMP1OK 0 (ARROK)ARROK 0 (UP)UP 0 (DOWN)DOWN 0 (UE)UE 0 (REPOK)REPOK 0 (B_0x0)CC2IF 0 (CMP2OK)CMP2OK 0 (DIEROK)DIEROK

CC2IF=B_0x0, CC1IF=B_0x0

Description

LPTIM1 interrupt and status register [alternate]

Fields

CC1IF

Compare 1 interrupt flag

0 (B_0x0): No match

1 (B_0x1): The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR1 register’s value
ARRM

Autoreload match
EXTTRIG

External trigger edge event
CMP1OK

Compare register 1 update OK
ARROK

Autoreload register update OK
UP

Counter direction change down to up
DOWN

Counter direction change up to down
UE

LPTIM update event occurred
REPOK

Repetition register update OK
CC2IF

Compare 2 interrupt flag

0 (B_0x0): No match

1 (B_0x1): The content of the counter LPTIM_CNT register value has matched the LPTIM_CCR2 register’s value
CMP2OK

Compare register 2 update OK
DIEROK

Interrupt enable register update OK

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32