WAVPOL=B_0x0, TRGFLT=B_0x0, CKPOL=B_0x0, TRIGSEL=B_0x0, PRELOAD=B_0x0, TRIGEN=B_0x0, CKSEL=B_0x0, CKFLT=B_0x0, ENC=B_0x0, PRESC=B_0x0, WAVE=B_0x0, TIMOUT=B_0x0, COUNTMODE=B_0x0
LPTIM5 configuration register
| CKSEL | Clock selector 0 (B_0x0): LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) 1 (B_0x1): LPTIM is clocked by an external clock source through the LPTIM external Input1 |
| CKPOL | Clock Polarity 0 (B_0x0): the rising edge is the active edge used for counting. 1 (B_0x1): the falling edge is the active edge used for counting. 2 (B_0x2): both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. 3 (B_0x3): not allowed |
| CKFLT | Configurable digital filter for external clock 0 (B_0x0): any external clock signal level change is considered as a valid transition 1 (B_0x1): external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 2 (B_0x2): external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 3 (B_0x3): external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. |
| TRGFLT | Configurable digital filter for trigger 0 (B_0x0): any trigger active level change is considered as a valid trigger 1 (B_0x1): trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 2 (B_0x2): trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 3 (B_0x3): trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. |
| PRESC | Clock prescaler 0 (B_0x0): /1 1 (B_0x1): /2 2 (B_0x2): /4 3 (B_0x3): /8 4 (B_0x4): /16 5 (B_0x5): /32 6 (B_0x6): /64 7 (B_0x7): /128 |
| TRIGSEL | Trigger selector 0 (B_0x0): lptim_ext_trig0 1 (B_0x1): lptim_ext_trig1 2 (B_0x2): lptim_ext_trig2 3 (B_0x3): lptim_ext_trig3 4 (B_0x4): lptim_ext_trig4 5 (B_0x5): lptim_ext_trig5 6 (B_0x6): lptim_ext_trig6 7 (B_0x7): lptim_ext_trig7 |
| TRIGEN | Trigger enable and polarity 0 (B_0x0): software trigger (counting start is initiated by software) 1 (B_0x1): rising edge is the active edge 2 (B_0x2): falling edge is the active edge 3 (B_0x3): both edges are active edges |
| TIMOUT | Timeout enable 0 (B_0x0): A trigger event arriving when the timer is already started is ignored 1 (B_0x1): A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter |
| WAVE | Waveform shape 0 (B_0x0): Deactivate Set-once mode 1 (B_0x1): Activate the Set-once mode |
| WAVPOL | Waveform shape polarity 0 (B_0x0): The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CCRx registers 1 (B_0x1): The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CCRx registers |
| PRELOAD | Registers update mode 0 (B_0x0): Registers are updated after each APB bus write access 1 (B_0x1): Registers are updated at the end of the current LPTIM period |
| COUNTMODE | counter mode enabled 0 (B_0x0): the counter is incremented following each internal clock pulse 1 (B_0x1): the counter is incremented following each valid clock pulse on the LPTIM external Input1 |
| ENC | Encoder mode enable 0 (B_0x0): Encoder mode disabled 1 (B_0x1): Encoder mode enabled |