FUIF=B_0x0, RRIF=B_0x0, TERRIF=B_0x0, CRCIF=B_0x0, FUWIF=B_0x0, LIF=B_0x0
LTDC interrupt status register 2
| LIF | Line interrupt flag 0 (B_0x0): no line interrupt generated 1 (B_0x1): line interrupt generated when a programmed line is reached |
| FUWIF | FIFO underrun warning interrupt flag 0 (B_0x0): no FIFO underrun warning interrupt generated. 1 (B_0x1): FIFO underrun warning interrupt generated, if one of the layer FIFO is empty and pixel data is read from the FIFO |
| TERRIF | Transfer error interrupt flag 0 (B_0x0): no transfer error interrupt generated 1 (B_0x1): transfer error interrupt generated when a bus error occurs |
| RRIF | Register reload interrupt flag 0 (B_0x0): no register reload interrupt generated 1 (B_0x1): register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) |
| FUIF | FIFO underrun interrupt flag 0 (B_0x0): no FIFO underrun interrupt generated. 1 (B_0x1): FIFO underrun interrupt generated, if one of the layer FIFO is empty and many pixel data are read from the FIFO |
| CRCIF | CRC Error interrupt flag 0 (B_0x0): no CRC error interrupt generated 1 (B_0x1): CRC error interrupt generated when a bus error occurs |