OF=B_0x0, CBF=B_0x0, YF=B_0x0, YCM=B_0x0, YCEN=B_0x0, YREN=B_0x0
LTDC layerx planar configuration register
| YCEN | YCbCr-to-RGB conversion enable 0 (B_0x0): conversion disabled 1 (B_0x1): YCbCr conversion enabled, using the YCM setting above |
| YCM | YCbCr conversion mode 0 (B_0x0): interleaved 422 (Cb and Cr component are replicated horizontally for pixels P and P+1) 1 (B_0x1): semi-Planar 420: (Cb and Cr component are replicated horizontally and vertically.The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers). 2 (B_0x2): full-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers). |
| YF | Y component first 0 (B_0x0): Y component disabled (thus Cr or Cb component is on byte 0) 1 (B_0x1): Y component enabled (thus Y component is on byte 0) |
| CBF | Cb component first 0 (B_0x0): Cb disabled (thus Cr component is on byte 0 and 1) 1 (B_0x1): Cb enabled (thus Cb component is on byte 0 and 1) |
| OF | Odd pixel first 0 (B_0x0): odd pixel disabled (thus even pixel on byte 0) 1 (B_0x1): odd pixel enabled (thus odd pixel on byte 0) |
| YREN | Y rescale enable for the color dynamic range 0 (B_0x0): rescaling disabled (input component thus assumed provided in 0 to 255) 1 (B_0x1): rescaling enabled (input component thus assumed provided in 16 to 235). |