Regviz

stm32 /stm32n6 /STM32N647 /LTDC /LTDC_SRCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as LTDC_SRCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32n6/STM32N645/LTDC/LTDC_SRCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)IMR 0 (B_0x0)VBR

VBR=B_0x0, IMR=B_0x0

Description

LTDC shadow reload configuration register

Fields

IMR

immediate reload trigger

0 (B_0x0): no effect

1 (B_0x1): The shadow registers are reloaded immediately.
VBR

vertical blanking reload request

0 (B_0x0): no effect

1 (B_0x1): The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area).

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32