stm32 /stm32n6 /STM32N647 /OTG1 /OTG_HCCHAR10

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Interpret as OTG_HCCHAR10

31282724232019161512118743000000000000000000000000000000000000000000MPSIZ0EPNUM0 (B_0x0)EPDIR0 (LSDEV)LSDEV0 (B_0x0)EPTYP0MCNT0DAD0 (B_0x0)ODDFRM0 (CHDIS)CHDIS0 (B_0x0)CHENA

CHENA=B_0x0, ODDFRM=B_0x0, EPDIR=B_0x0, EPTYP=B_0x0

Description

OTG host channel 10 characteristics register

Fields

MPSIZ

Maximum packet size

EPNUM

Endpoint number

EPDIR

Endpoint direction

0 (B_0x0): OUT

1 (B_0x1): IN

LSDEV

Low-speed device

EPTYP

Endpoint type

0 (B_0x0): Control

1 (B_0x1): Isochronous

2 (B_0x2): Bulk

3 (B_0x3): Interrupt

MCNT

Multicount

1 (B_0x1): 1 transaction

2 (B_0x2): 2 transactions per frame to be issued for this endpoint

3 (B_0x3): 3 transactions per frame to be issued for this endpoint

DAD

Device address

ODDFRM

Odd frame

0 (B_0x0): Even frame

1 (B_0x1): Odd frame

CHDIS

Channel disable

CHENA

Channel enable

0 (B_0x0): Channel disabled

1 (B_0x1): Channel enabled

Links

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