stm32 /stm32n6 /STM32N647 /PWR /PWR_CPUCR

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Interpret as PWR_CPUCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)PDDS 0 (B_0x0)CSSF 0 (B_0x0)STOPF 0 (B_0x0)SBF 0 (B_0x0)SVOS

CSSF=B_0x0, STOPF=B_0x0, SBF=B_0x0, PDDS=B_0x0, SVOS=B_0x0

Description

PWR CPU control register

Fields

PDDS

Power-down deepsleep selection

0 (B_0x0): Stop mode when device enters deepsleep

1 (B_0x1): Standby mode when device enters deepsleep

CSSF

Clear Standby and Stop flags (always read as 0)

0 (B_0x0): No effect

1 (B_0x1): When written, clear the CPU flags (STOPF, SBF).

STOPF

Stop flag

0 (B_0x0): System has not been in Stop mode.

1 (B_0x1): System has been in Stop mode.

SBF

Standby flag

0 (B_0x0): System has not been in Standby mode.

1 (B_0x1): System has been in Standby mode.

SVOS

System Stop mode voltage scaling selection

0 (B_0x0): SVOS low

1 (B_0x1): SVOS high (default)

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