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stm32 /stm32n6 /STM32N647 /PWR /PWR_CR2

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Interpret as PWR_CR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)PVDEN 0 (B_0x0)PVDO

PVDO=B_0x0, PVDEN=B_0x0

Description

PWR control register 2

Fields

PVDEN

Programmable voltage detector enable

0 (B_0x0): PVD disabled

1 (B_0x1): PVD enabled
PVDO

Programmable voltage detect output

0 (B_0x0): Voltage level on PVD_IN is equal or higher than the internal VREFINT.

1 (B_0x1): Voltage level on PVD_IN is lower than the internal VREFINT.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32