stm32 /stm32n6 /STM32N647 /RCC /RCC_AHB5RSTCR

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Interpret as RCC_AHB5RSTCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (HPDMA1RSTC)HPDMA1RSTC 0 (DMA2DRSTC)DMA2DRSTC 0 (JPEGRSTC)JPEGRSTC 0 (FMCRSTC)FMCRSTC 0 (XSPI1RSTC)XSPI1RSTC 0 (PSSIRSTC)PSSIRSTC 0 (SDMMC2RSTC)SDMMC2RSTC 0 (SDMMC1RSTC)SDMMC1RSTC 0 (XSPI2RSTC)XSPI2RSTC 0 (XSPIMRSTC)XSPIMRSTC 0 (XSPI3RSTC)XSPI3RSTC 0 (MCE4RSTC)MCE4RSTC 0 (GFXMMURSTC)GFXMMURSTC 0 (GPURSTC)GPURSTC 0 (SYSCFGOTGHSPHY1RSTC)SYSCFGOTGHSPHY1RSTC 0 (SYSCFGOTGHSPHY2RSTC)SYSCFGOTGHSPHY2RSTC 0 (ETH1RSTC)ETH1RSTC 0 (OTG1RSTC)OTG1RSTC 0 (OTGPHY1RSTC)OTGPHY1RSTC 0 (OTGPHY2RSTC)OTGPHY2RSTC 0 (OTG2RSTC)OTG2RSTC 0 (NPUCACHERSTC)NPUCACHERSTC 0 (NPURSTC)NPURSTC

Description

RCC AHB5 reset register

Fields

HPDMA1RSTC

HPDMA1 reset

DMA2DRSTC

DMA2D reset

JPEGRSTC

JPEG reset

FMCRSTC

FMC reset

XSPI1RSTC

XSPI1 reset

PSSIRSTC

PSSI reset

SDMMC2RSTC

SDMMC2 reset

SDMMC1RSTC

SDMMC1 reset

XSPI2RSTC

XSPI2 reset

XSPIMRSTC

XSPIM reset

XSPI3RSTC

XSPI3 reset

MCE4RSTC

MCE4 reset

GFXMMURSTC

GFXMMU reset

GPURSTC

GPU reset

SYSCFGOTGHSPHY1RSTC

SYSCFGOTGHSPHY1 reset

SYSCFGOTGHSPHY2RSTC

SYSCFGOTGHSPHY2 reset

ETH1RSTC

ETH1 reset

OTG1RSTC

OTG1 reset

OTGPHY1RSTC

OTGPHY1 reset

OTGPHY2RSTC

OTGPHY2 reset

OTG2RSTC

OTG2 reset

NPUCACHERSTC

NPUCACHE reset

NPURSTC

NPU reset

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