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stm32 /stm32n6 /STM32N647 /RCC /RCC_APB1HENR

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Interpret as RCC_APB1HENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)MDIOSEN 0 (B_0x0)FDCANEN 0 (B_0x0)UCPD1EN

UCPD1EN=B_0x0, FDCANEN=B_0x0, MDIOSEN=B_0x0

Description

RCC APB1H enable register

Fields

MDIOSEN

MDIOS enable

0 (B_0x0): MDIOS is disabled (default after reset)

1 (B_0x1): MDIOS is enabled
FDCANEN

FDCAN enable

0 (B_0x0): FDCAN is disabled (default after reset)

1 (B_0x1): FDCAN is enabled
UCPD1EN

UCPD1 enable

0 (B_0x0): UCPD1 is disabled (default after reset)

1 (B_0x1): UCPD1 is enabled

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32