UART5RST=B_0x0, TIM7RST=B_0x0, SPI2RST=B_0x0, UART8RST=B_0x0, TIM5RST=B_0x0, TIM3RST=B_0x0, I2C2RST=B_0x0, TIM4RST=B_0x0, TIM2RST=B_0x0, I2C3RST=B_0x0, USART2RST=B_0x0, TIM11RST=B_0x0, USART3RST=B_0x0, LPTIM1RST=B_0x0, UART4RST=B_0x0, TIM13RST=B_0x0, SPI3RST=B_0x0, TIM10RST=B_0x0, TIM12RST=B_0x0, TIM14RST=B_0x0, TIM6RST=B_0x0, I3C1RST=B_0x0, I3C2RST=B_0x0, WWDGRST=B_0x0, I2C1RST=B_0x0, SPDIFRX1RST=B_0x0, UART7RST=B_0x0
RCC APB1L reset register
| TIM2RST | TIM2 reset 0 (B_0x0): TIM2 is not under reset (default after reset) 1 (B_0x1): TIM2 is under reset |
| TIM3RST | TIM3 reset 0 (B_0x0): TIM3 is not under reset (default after reset) 1 (B_0x1): TIM3 is under reset |
| TIM4RST | TIM4 reset 0 (B_0x0): TIM4 is not under reset (default after reset) 1 (B_0x1): TIM4 is under reset |
| TIM5RST | TIM5 reset 0 (B_0x0): TIM5 is not under reset (default after reset) 1 (B_0x1): TIM5 is under reset |
| TIM6RST | TIM6 reset 0 (B_0x0): TIM6 is not under reset (default after reset) 1 (B_0x1): TIM6 is under reset |
| TIM7RST | TIM7 reset 0 (B_0x0): TIM7 is not under reset (default after reset) 1 (B_0x1): TIM7 is under reset |
| TIM12RST | TIM12 reset 0 (B_0x0): TIM12 is not under reset (default after reset) 1 (B_0x1): TIM12 is under reset |
| TIM13RST | TIM13 reset 0 (B_0x0): TIM13 is not under reset (default after reset) 1 (B_0x1): TIM13 is under reset |
| TIM14RST | TIM14 reset 0 (B_0x0): TIM14 is not under reset (default after reset) 1 (B_0x1): TIM14 is under reset |
| LPTIM1RST | LPTIM1 reset 0 (B_0x0): LPTIM1 is not under reset (default after reset) 1 (B_0x1): LPTIM1 is under reset |
| WWDGRST | WWDG reset 0 (B_0x0): WWDG is not under reset (default after reset) 1 (B_0x1): WWDG is under reset |
| TIM10RST | TIM10 reset 0 (B_0x0): TIM10 is not under reset (default after reset) 1 (B_0x1): TIM10 is under reset |
| TIM11RST | TIM11 reset 0 (B_0x0): TIM11 is not under reset (default after reset) 1 (B_0x1): TIM11 is under reset |
| SPI2RST | SPI2 reset 0 (B_0x0): SPI2 is not under reset (default after reset) 1 (B_0x1): SPI2 is under reset |
| SPI3RST | SPI3 reset 0 (B_0x0): SPI3 is not under reset (default after reset) 1 (B_0x1): SPI3 is under reset |
| SPDIFRX1RST | SPDIFRX1 reset 0 (B_0x0): SPDIFRX1 is not under reset (default after reset) 1 (B_0x1): SPDIFRX1 is under reset |
| USART2RST | USART2 reset 0 (B_0x0): USART2 is not under reset (default after reset) 1 (B_0x1): USART2 is under reset |
| USART3RST | USART3 reset 0 (B_0x0): USART3 is not under reset (default after reset) 1 (B_0x1): USART3 is under reset |
| UART4RST | UART4 reset 0 (B_0x0): UART4 is not under reset (default after reset) 1 (B_0x1): UART4 is under reset |
| UART5RST | UART5 reset 0 (B_0x0): UART5 is not under reset (default after reset) 1 (B_0x1): UART5 is under reset |
| I2C1RST | I2C1 reset 0 (B_0x0): I2C1 is not under reset (default after reset) 1 (B_0x1): I2C1 is under reset |
| I2C2RST | I2C2 reset 0 (B_0x0): I2C2 is not under reset (default after reset) 1 (B_0x1): I2C2 is under reset |
| I2C3RST | I2C3 reset 0 (B_0x0): I2C3 is not under reset (default after reset) 1 (B_0x1): I2C3 is under reset |
| I3C1RST | I3C1 reset 0 (B_0x0): I3C1 is not under reset (default after reset) 1 (B_0x1): I3C1 is under reset |
| I3C2RST | I3C2 reset 0 (B_0x0): I3C2 is not under reset (default after reset) 1 (B_0x1): I3C2 is under reset |
| UART7RST | UART7 reset 0 (B_0x0): UART7 is not under reset (default after reset) 1 (B_0x1): UART7 is under reset |
| UART8RST | UART8 reset 0 (B_0x0): UART8 is not under reset (default after reset) 1 (B_0x1): UART8 is under reset |