Regviz

stm32 /stm32n6 /STM32N647 /RCC /RCC_APB3LPENR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RCC_APB3LPENR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32n6/STM32N645/RCC/RCC_APB3LPENR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DFTLPEN

DFTLPEN=B_0x0

Description

RCC APB3 Sleep enable register

Fields

DFTLPEN

DFT sleep enable

0 (B_0x0): DFT is disabled in Sleep mode (default after reset)

1 (B_0x1): DFT is enabled in Sleep mode

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32