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stm32 /stm32n6 /STM32N647 /RCC /RCC_APB5RSTR

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Interpret as RCC_APB5RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LTDCRST 0 (B_0x0)DCMIPPRST 0 (B_0x0)GFXTIMRST 0 (B_0x0)VENCRST 0 (B_0x0)CSIRST

GFXTIMRST=B_0x0, LTDCRST=B_0x0, CSIRST=B_0x0, VENCRST=B_0x0, DCMIPPRST=B_0x0

Description

RCC APB5 reset register

Fields

LTDCRST

LTDC reset

0 (B_0x0): LTDC is not under reset (default after reset)

1 (B_0x1): LTDC is under reset
DCMIPPRST

DCMIPP reset

0 (B_0x0): DCMIPP is not under reset (default after reset)

1 (B_0x1): DCMIPP is under reset
GFXTIMRST

GFXTIM reset

0 (B_0x0): GFXTIM is not under reset (default after reset)

1 (B_0x1): GFXTIM is under reset
VENCRST

VENC reset

0 (B_0x0): VENC is not under reset (default after reset)

1 (B_0x1): VENC is under reset
CSIRST

CSI reset

0 (B_0x0): CSI is not under reset (default after reset)

1 (B_0x1): CSI is under reset

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32