ETH1PTPDIV=B_0x0, ETH1GTXCLKSEL=B_0x0, ETH1CLKSEL=B_0x0, ETH1PTPSEL=B_0x0, ETH1PWRDOWNACK=B_0x0
RCC clock configuration for independent peripheral register 2
| ETH1PTPSEL | Source selection for the ETH1 kernel clock 0 (B_0x0): hclke selected as reference clock 1 (B_0x1): per_ck selected as reference clock 2 (B_0x2): ic13_ck selected as reference clock 3 (B_0x3): hse_ck selected as reference clock |
| ETH1PTPDIV | ETH1 Kernel clock divider selection (for clock ck_ker_eth1ptp) 0 (B_0x0): ck_ker_eth1ptp is divided by 1 1 (B_0x1): ck_ker_eth1ptp is divided by 2 2 (B_0x2): ck_ker_eth1ptp is divided by 3 3 (B_0x3): ck_ker_eth1ptp is divided by 4 15 (B_0xF): ck_ker_eth1ptp is divided by 16 |
| ETH1PWRDOWNACK | Set and reset by software. 0 (B_0x0): Power-down sequence start not yet acknowledged. 1 (B_0x1): Power-down sequence start acknowledged |
| ETH1CLKSEL | Source selection for the ETH1 kernel clock 0 (B_0x0): hclke selected as reference clock 1 (B_0x1): per_ck selected as reference clock 2 (B_0x2): ic12_ck selected as reference clock 3 (B_0x3): hse_ck selected as reference clock |
| ETH1SEL | Set and reset by software |
| ETH1REFCLKSEL | Set and reset by software |
| ETH1GTXCLKSEL | Set and reset by software. 0 (B_0x0): MII 1 (B_0x1): RGMII |