OTGPHY1SEL=B_0x0, XSPI3SEL=B_0x0, XSPI1SEL=B_0x0, OTGPHY2SEL=B_0x0, XSPI2SEL=B_0x0
RCC clock configuration for independent peripheral register6
| XSPI1SEL | Source selection for the XSPI1 kernel clock 0 (B_0x0): hclk5 selected as reference clock 1 (B_0x1): per_ck selected as reference clock 2 (B_0x2): ic3_ck selected as reference clock 3 (B_0x3): ic4_ck selected as reference clock |
| XSPI2SEL | Source selection for the XSPI2 kernel clock 0 (B_0x0): hclk5 selected as reference clock 1 (B_0x1): per_ck selected as reference clock 2 (B_0x2): ic3_ck selected as reference clock 3 (B_0x3): ic4_ck selected as reference clock |
| XSPI3SEL | Source selection for the XSPI3 kernel clock 0 (B_0x0): hclk5 selected as reference clock 1 (B_0x1): per_ck selected as reference clock 2 (B_0x2): ic3_ck selected as reference clock 3 (B_0x3): ic4_ck selected as reference clock |
| OTGPHY1SEL | Source selection for the OTGPHY1 kernel clock 0 (B_0x0): hse_ck selected as reference clock 1 (B_0x1): per_ck selected as reference clock 2 (B_0x2): ic15_ck selected as reference clock 3 (B_0x3): hse_div2_osc_ck selected as reference clock |
| OTGPHY1CKREFSEL | Set and reset by software |
| OTGPHY2SEL | Source selection for the OTGPHY2 kernel clock 0 (B_0x0): hse_ck selected as reference clock 1 (B_0x1): per_ck selected as reference clock 2 (B_0x2): ic15_ck selected as reference clock 3 (B_0x3): hse_div2_osc_ck selected as reference clock |
| OTGPHY2CKREFSEL | Set and reset by software |