LSIRDYIE=B_0x0, HSIRDYIE=B_0x0, PLL1RDYIE=B_0x0, PLL2RDYIE=B_0x0, HSERDYIE=B_0x0, WKUPIE=B_0x0, MSIRDYIE=B_0x0, LSERDYIE=B_0x0, PLL3RDYIE=B_0x0, LSECSSIE=B_0x0, PLL4RDYIE=B_0x0, HSECSSIE=B_0x0
RCC clock-source interrupt enable register
| LSIRDYIE | LSI ready interrupt enable 0 (B_0x0): LSI ready interrupt disabled (default after reset) 1 (B_0x1): LSI ready interrupt enabled |
| LSERDYIE | LSE ready interrupt enable 0 (B_0x0): LSE ready interrupt disabled (default after reset) 1 (B_0x1): LSE ready interrupt enabled |
| MSIRDYIE | MSI ready interrupt enable 0 (B_0x0): MSI ready interrupt disabled (default after reset) 1 (B_0x1): MSI ready interrupt enabled |
| HSIRDYIE | HSI ready interrupt enable 0 (B_0x0): HSI ready interrupt disabled (default after reset) 1 (B_0x1): HSI ready interrupt enabled |
| HSERDYIE | HSE ready interrupt enable 0 (B_0x0): HSE ready interrupt disabled (default after reset) 1 (B_0x1): HSE ready interrupt enabled |
| PLL1RDYIE | PLL1 ready interrupt enable 0 (B_0x0): PLL1 lock interrupt disabled (default after reset) 1 (B_0x1): PLL1 lock interrupt enabled |
| PLL2RDYIE | PLL2 ready interrupt enable 0 (B_0x0): PLL2 lock interrupt disabled (default after reset) 1 (B_0x1): PLL2 lock interrupt enabled |
| PLL3RDYIE | PLL3 ready interrupt enable 0 (B_0x0): PLL3 lock interrupt disabled (default after reset) 1 (B_0x1): PLL3 lock interrupt enabled |
| PLL4RDYIE | PLL4 ready interrupt enable 0 (B_0x0): PLL4 lock interrupt disabled (default after reset) 1 (B_0x1): PLL4 lock interrupt enabled |
| LSECSSIE | LSE clock security system (CSS) interrupt enable 0 (B_0x0): LSE CSS interrupt disabled (default after reset) 1 (B_0x1): LSE CSS interrupt enabled |
| HSECSSIE | HSE clock security system (CSS) interrupt enable 0 (B_0x0): HSE CSS interrupt disabled 1 (B_0x1): HSE CSS interrupt enabled (default after reset) |
| WKUPIE | CPU wakeup from Stop interrupt enable 0 (B_0x0): Wakeup interrupt disabled (default after reset) 1 (B_0x1): Wakeup interrupt enabled |