HSEDIV2BYP=B_0x0, HSEEXT=B_0x0, HSECSSD=B_0x0, HSEBYP=B_0x0, HSECSSRA=B_0x0, HSECSSBPRE=B_0x0, HSEDRV=B_0x0, HSECSSBYP=B_0x0, HSECSSON=B_0x0, HSEGFON=B_0x0
RCC HSE configuration register
| HSEDIV2BYP | HSE div2 oscillator clock in Bypass mode 0 (B_0x0): HSE: hse_div2_osc_ck = hse_osc_ck/2 (default after reset) 1 (B_0x1): HSE: hse_div2_osc_ck = hse_osc_ck |
| HSECSSON | HSE clock security system (CSS) enable 0 (B_0x0): clock Security System on the HSE oscillator OFF (default after reset) 1 (B_0x1): clock Security System on the HSE oscillator ON |
| HSECSSRA | HSE clock security system (CSS) re-arm function 0 (B_0x0): Writing 0 has no effect (default after reset) 1 (B_0x1): Writing 1 generates a re-arm pulse for the HSECSS function |
| HSECSSD | HSE clock security system (CSS) failure detection 0 (B_0x0): No failure detected on the oscillator (default after reset) 1 (B_0x1): Failure detected on the oscillator |
| HSECSSBYP | HSE clock security system (CSS) bypass enable 0 (B_0x0): clock Security System Bypass of the HSE oscillator is OFF (default after reset) 1 (B_0x1): clock Security System Bypass on the HSE oscillator is ON |
| HSECSSBPRE | HSE clock security system (CSS) bypass divider 0 (B_0x0): HSI clock is divided by 1 1 (B_0x1): HSI clock is divided by 2 (default after reset) 2 (B_0x2): HSI clock is divided by 3 3 (B_0x3): HSI clock is divided by 4 15 (B_0xF): HSI clock is divided by 15 |
| HSEBYP | HSE clock bypass 0 (B_0x0): HSE oscillator not bypassed (default after reset) 1 (B_0x1): HSE oscillator bypassed with an external clock |
| HSEEXT | HSE clock type in Bypass mode 0 (B_0x0): HSE in analog mode (default after reset) 1 (B_0x1): HSE in digital mode |
| HSEGFON | HSE clock glitch filter enable 0 (B_0x0): LSE clock glitch filter is disabled (default after reset) 1 (B_0x1): LSE clock glitch filter is enabled |
| HSEDRV | HSE oscillator driving capability 0 (B_0x0): Lowest drive (default after reset) 1 (B_0x1): Medium low drive 2 (B_0x2): Medium high drive 3 (B_0x3): Highest drive |