LSEBYP=B_0x0, LSEDRV=B_0x0, LSECSSD=B_0x0, LSECSSON=B_0x0, LSECSSRA=B_0x0, LSEEXT=B_0x0, LSEGFON=B_0x0
RCC LSE configuration register
| LSECSSON | LSE clock security system (CSS) enable 0 (B_0x0): clock Security System on the LSE oscillator OFF (default after reset) 1 (B_0x1): clock Security System on the LSE oscillator ON |
| LSECSSRA | LSE clock security system (CSS) re-arm function 0 (B_0x0): Writing 0 has no effect (default after reset) 1 (B_0x1): Writing 1 generates a re-arm pulse for the LSECSS function |
| LSECSSD | LSE clock security system (CSS) failure detection 0 (B_0x0): No failure detected on the oscillator (default after reset) 1 (B_0x1): Failure detected on the oscillator |
| LSEBYP | LSE clock bypass 0 (B_0x0): LSE oscillator not bypassed (default after reset) 1 (B_0x1): LSE oscillator bypassed with an external clock |
| LSEEXT | LSE clock type in Bypass mode 0 (B_0x0): LSE in analog mode (default after reset) 1 (B_0x1): LSE in digital mode |
| LSEGFON | LSE clock glitch filter enable 0 (B_0x0): LSE clock glitch filter is disabled (default after reset) 1 (B_0x1): LSE clock glitch filter is enabled |
| LSEDRV | LSE oscillator driving capability 0 (B_0x0): Lowest drive (default after reset) 1 (B_0x1): Medium low drive 2 (B_0x2): Medium high drive 3 (B_0x3): Highest drive |