PLL3MODSPRDW=B_0x0, PLL3PDIVEN=B_0x0, PLL3PDIV1=B_0x0, PLL3DACEN=B_0x0, PLL3MODSSRST=B_0x0, PLL3MODSSDIS=B_0x0, PLL3MODDSEN=B_0x0, PLL3PDIV2=B_0x0
RCC PLL3 configuration register 3
| PLL3MODSSRST | PLL3 Modulation Spread Spectrum reset 0 (B_0x0): The PLL3 modulation Spread Spectrum reset module is released 1 (B_0x1): The PLL3 modulation Spread Spectrum reset module is asserted (default after reset) |
| PLL3DACEN | PLL3 noise canceling DAC enable in fractional mode. 0 (B_0x0): DAC is not active (default after reset) 1 (B_0x1): DAC is active |
| PLL3MODSSDIS | PLL3 Modulation Spread-Spectrum Disable 0 (B_0x0): Modulation Spread-Spectrum is active (and Fractional Divide inactive) 1 (B_0x1): Fractional Divide is active (and the Modulation Spread-Spectrum inactive) (default after reset) |
| PLL3MODDSEN | PLL3 Modulation Spread-Spectrum (and Fractional Divide) enable 0 (B_0x0): Modulation Spread-Spectrum and Fractional Divide are not active (default after reset) 1 (B_0x1): Modulation Spread-Spectrum and Fractional Divide are active |
| PLL3MODSPRDW | PLL3 Modulation Down Spread 0 (B_0x0): Center-spread modulation selected (default after reset) 1 (B_0x1): Down-spread modulation selected |
| PLL3MODDIV | PLL3 Modulation Division frequency adjustment |
| PLL3MODSPR | PLL3 Modulation Spread depth adjustment |
| PLL3PDIV2 | PLL3 VCO frequency divider level 2 0 (B_0x0): Not applicable 1 (B_0x1): VCO output is divided by 1 (minimum value) (default after reset) 7 (B_0x7): VCO output is divided by 7 |
| PLL3PDIV1 | PLL3 VCO frequency divider level 1 0 (B_0x0): Not applicable 1 (B_0x1): VCO output is divided by 1 (minimum value) (default after reset) 7 (B_0x7): VCO output is divided by 7 |
| PLL3PDIVEN | PLL3 post divider POSTDIV1, POSTDIV2, and PLL clock output enable 0 (B_0x0): POSTDIV1 and POSTDIV2 are powered down 1 (B_0x1): POSTDIV1 and POSTDIV2 dividers are active (default after reset) |