stm32 /stm32n6 /STM32N647 /RCC /RCC_PUBCFGCR5

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Interpret as RCC_PUBCFGCR5

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AXISRAM3PUBC)AXISRAM3PUBC 0 (AXISRAM4PUBC)AXISRAM4PUBC 0 (AXISRAM5PUBC)AXISRAM5PUBC 0 (AXISRAM6PUBC)AXISRAM6PUBC 0 (AHBSRAM1PUBC)AHBSRAM1PUBC 0 (AHBSRAM2PUBC)AHBSRAM2PUBC 0 (BKPSRAMPUBC)BKPSRAMPUBC 0 (AXISRAM1PUBC)AXISRAM1PUBC 0 (AXISRAM2PUBC)AXISRAM2PUBC 0 (FLEXRAMPUBC)FLEXRAMPUBC 0 (CACHEAXIRAMPUBC)CACHEAXIRAMPUBC 0 (VENCRAMPUBC)VENCRAMPUBC

Description

RCC public configuration register4

Fields

AXISRAM3PUBC

Defines the public protection of the AXISRAM3 configuration bits (enable, ready, divider).

AXISRAM4PUBC

Defines the public protection of the AXISRAM4 configuration bits (enable, ready, divider).

AXISRAM5PUBC

Defines the public protection of the AXISRAM5 configuration bits (enable, ready, divider).

AXISRAM6PUBC

Defines the public protection of the AXISRAM6 configuration bits (enable, ready, divider).

AHBSRAM1PUBC

Defines the public protection of the AHBSRAM1 configuration bits (enable, ready, divider).

AHBSRAM2PUBC

Defines the public protection of the AHBSRAM2 configuration bits (enable, ready, divider).

BKPSRAMPUBC

Defines the public protection of the BKPSRAM configuration bits (enable, ready, divider).

AXISRAM1PUBC

Defines the public protection of the AXISRAM1 configuration bits (enable, ready, divider).

AXISRAM2PUBC

Defines the public protection of the AXISRAM2 configuration bits (enable, ready, divider).

FLEXRAMPUBC

Defines the public protection of the FLEXRAM configuration bits (enable, ready, divider).

CACHEAXIRAMPUBC

Defines the public protection of the NPUCACHERAM configuration bits (enable, ready, divider).

VENCRAMPUBC

Defines the public protection of the VENCRAM configuration bits (enable, ready, divider).

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