MRD=B_0x0, EADLY=B_0x0
RCC APB5 Sleep enable register
| MRD | BOOTROM sleep enable 0 (B_0x0): No extra delay added by the BOOTROM 1 (B_0x1): 100 us 2 (B_0x2): 200 us 3 (B_0x3): 500 us 4 (B_0x4): 1 ms 5 (B_0x5): 2 ms 6 (B_0x6): 5 ms (default after reset) 7 (B_0x7): 10 ms 8 (B_0x8): 20 ms 9 (B_0x9): 50 ms 10 (B_0xA): 100 ms 11 (B_0xB): 200 ms 12 (B_0xC): 500 ms 13 (B_0xD): 1 s 14 (B_0xE): 2 s 15 (B_0xF): 5 s |
| EADLY | BOOTROM sleep enable 0 (B_0x0): sysrstn low pulse duration is guaranteed by the pulse stretcher of the PAD. The RPCTL is bypassed (default after reset) 1 (B_0x1): The guaranteed sysrstn low pulse duration is about 1 ms (1 x 32 lsi_ck cycles) 2 (B_0x2): The guaranteed sysrstn low pulse duration is about 2 ms (2 x 32 lsi_ck cycles) |