stm32 /stm32n6 /STM32N647 /RIFSC /RIFSC_PPSR3

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Interpret as RIFSC_PPSR3

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)PPEN96 0 (B_0x0)PPEN97 0 (B_0x0)PPEN98 0 (B_0x0)PPEN99 0 (B_0x0)PPEN100 0 (B_0x0)PPEN101 0 (B_0x0)PPEN102 0 (B_0x0)PPEN103 0 (B_0x0)PPEN104 0 (B_0x0)PPEN105 0 (B_0x0)PPEN106 0 (B_0x0)PPEN107 0 (B_0x0)PPEN108 0 (B_0x0)PPEN109 0 (B_0x0)PPEN110 0 (B_0x0)PPEN111 0 (B_0x0)PPEN112 0 (B_0x0)PPEN113 0 (B_0x0)PPEN114 0 (B_0x0)PPEN115 0 (B_0x0)PPEN116 0 (B_0x0)PPEN117 0 (B_0x0)PPEN118 0 (B_0x0)PPEN119 0 (B_0x0)PPEN120 0 (B_0x0)PPEN121 0 (B_0x0)PPEN122 0 (B_0x0)PPEN123 0 (B_0x0)PPEN124 0 (B_0x0)PPEN125 0 (B_0x0)PPEN126 0 (B_0x0)PPEN127

PPEN122=B_0x0, PPEN104=B_0x0, PPEN125=B_0x0, PPEN109=B_0x0, PPEN102=B_0x0, PPEN121=B_0x0, PPEN112=B_0x0, PPEN118=B_0x0, PPEN110=B_0x0, PPEN119=B_0x0, PPEN127=B_0x0, PPEN106=B_0x0, PPEN101=B_0x0, PPEN100=B_0x0, PPEN124=B_0x0, PPEN116=B_0x0, PPEN107=B_0x0, PPEN115=B_0x0, PPEN114=B_0x0, PPEN126=B_0x0, PPEN97=B_0x0, PPEN103=B_0x0, PPEN99=B_0x0, PPEN117=B_0x0, PPEN111=B_0x0, PPEN108=B_0x0, PPEN120=B_0x0, PPEN123=B_0x0, PPEN105=B_0x0, PPEN113=B_0x0, PPEN98=B_0x0, PPEN96=B_0x0

Description

RIFSC peripheral protection status register 3

Fields

PPEN96

peripheral protection enable 96

0 (B_0x0): SEC96, PRIV96, and RLOCK96 register bit not present.

1 (B_0x1): SEC96, PRIV96, and RLOCK96 register bit present.

PPEN97

peripheral protection enable 97

0 (B_0x0): SEC97, PRIV97, and RLOCK97 register bit not present.

1 (B_0x1): SEC97, PRIV97, and RLOCK97 register bit present.

PPEN98

peripheral protection enable 98

0 (B_0x0): SEC98, PRIV98, and RLOCK98 register bit not present.

1 (B_0x1): SEC98, PRIV98, and RLOCK98 register bit present.

PPEN99

peripheral protection enable 99

0 (B_0x0): SEC99, PRIV99, and RLOCK99 register bit not present.

1 (B_0x1): SEC99, PRIV99, and RLOCK99 register bit present.

PPEN100

peripheral protection enable 100

0 (B_0x0): SEC100, PRIV100, and RLOCK100 register bit not present.

1 (B_0x1): SEC100, PRIV100, and RLOCK100 register bit present.

PPEN101

peripheral protection enable 101

0 (B_0x0): SEC101, PRIV101, and RLOCK101 register bit not present.

1 (B_0x1): SEC101, PRIV101, and RLOCK101 register bit present.

PPEN102

peripheral protection enable 102

0 (B_0x0): SEC102, PRIV102, and RLOCK102 register bit not present.

1 (B_0x1): SEC102, PRIV102, and RLOCK102 register bit present.

PPEN103

peripheral protection enable 103

0 (B_0x0): SEC103, PRIV103, and RLOCK103 register bit not present.

1 (B_0x1): SEC103, PRIV103, and RLOCK103 register bit present.

PPEN104

peripheral protection enable 104

0 (B_0x0): SEC104, PRIV104, and RLOCK104 register bit not present.

1 (B_0x1): SEC104, PRIV104, and RLOCK104 register bit present.

PPEN105

peripheral protection enable 105

0 (B_0x0): SEC105, PRIV105, and RLOCK105 register bit not present.

1 (B_0x1): SEC105, PRIV105, and RLOCK105 register bit present.

PPEN106

peripheral protection enable 106

0 (B_0x0): SEC106, PRIV106, and RLOCK106 register bit not present.

1 (B_0x1): SEC106, PRIV106, and RLOCK106 register bit present.

PPEN107

peripheral protection enable 107

0 (B_0x0): SEC107, PRIV107, and RLOCK107 register bit not present.

1 (B_0x1): SEC107, PRIV107, and RLOCK107 register bit present.

PPEN108

peripheral protection enable 108

0 (B_0x0): SEC108, PRIV108, and RLOCK108 register bit not present.

1 (B_0x1): SEC108, PRIV108, and RLOCK108 register bit present.

PPEN109

peripheral protection enable 109

0 (B_0x0): SEC109, PRIV109, and RLOCK109 register bit not present.

1 (B_0x1): SEC109, PRIV109, and RLOCK109 register bit present.

PPEN110

peripheral protection enable 110

0 (B_0x0): SEC110, PRIV110, and RLOCK110 register bit not present.

1 (B_0x1): SEC110, PRIV110, and RLOCK110 register bit present.

PPEN111

peripheral protection enable 111

0 (B_0x0): SEC111, PRIV111, and RLOCK111 register bit not present.

1 (B_0x1): SEC111, PRIV111, and RLOCK111 register bit present.

PPEN112

peripheral protection enable 112

0 (B_0x0): SEC112, PRIV112, and RLOCK112 register bit not present.

1 (B_0x1): SEC112, PRIV112, and RLOCK112 register bit present.

PPEN113

peripheral protection enable 113

0 (B_0x0): SEC113, PRIV113, and RLOCK113 register bit not present.

1 (B_0x1): SEC113, PRIV113, and RLOCK113 register bit present.

PPEN114

peripheral protection enable 114

0 (B_0x0): SEC114, PRIV114, and RLOCK114 register bit not present.

1 (B_0x1): SEC114, PRIV114, and RLOCK114 register bit present.

PPEN115

peripheral protection enable 115

0 (B_0x0): SEC115, PRIV115, and RLOCK115 register bit not present.

1 (B_0x1): SEC115, PRIV115, and RLOCK115 register bit present.

PPEN116

peripheral protection enable 116

0 (B_0x0): SEC116, PRIV116, and RLOCK116 register bit not present.

1 (B_0x1): SEC116, PRIV116, and RLOCK116 register bit present.

PPEN117

peripheral protection enable 117

0 (B_0x0): SEC117, PRIV117, and RLOCK117 register bit not present.

1 (B_0x1): SEC117, PRIV117, and RLOCK117 register bit present.

PPEN118

peripheral protection enable 118

0 (B_0x0): SEC118, PRIV118, and RLOCK118 register bit not present.

1 (B_0x1): SEC118, PRIV118, and RLOCK118 register bit present.

PPEN119

peripheral protection enable 119

0 (B_0x0): SEC119, PRIV119, and RLOCK119 register bit not present.

1 (B_0x1): SEC119, PRIV119, and RLOCK119 register bit present.

PPEN120

peripheral protection enable 120

0 (B_0x0): SEC120, PRIV120, and RLOCK120 register bit not present.

1 (B_0x1): SEC120, PRIV120, and RLOCK120 register bit present.

PPEN121

peripheral protection enable 121

0 (B_0x0): SEC121, PRIV121, and RLOCK121 register bit not present.

1 (B_0x1): SEC121, PRIV121, and RLOCK121 register bit present.

PPEN122

peripheral protection enable 122

0 (B_0x0): SEC122, PRIV122, and RLOCK122 register bit not present.

1 (B_0x1): SEC122, PRIV122, and RLOCK122 register bit present.

PPEN123

peripheral protection enable 123

0 (B_0x0): SEC123, PRIV123, and RLOCK123 register bit not present.

1 (B_0x1): SEC123, PRIV123, and RLOCK123 register bit present.

PPEN124

peripheral protection enable 124

0 (B_0x0): SEC124, PRIV124, and RLOCK124 register bit not present.

1 (B_0x1): SEC124, PRIV124, and RLOCK124 register bit present.

PPEN125

peripheral protection enable 125

0 (B_0x0): SEC125, PRIV125, and RLOCK125 register bit not present.

1 (B_0x1): SEC125, PRIV125, and RLOCK125 register bit present.

PPEN126

peripheral protection enable 126

0 (B_0x0): SEC126, PRIV126, and RLOCK126 register bit not present.

1 (B_0x1): SEC126, PRIV126, and RLOCK126 register bit present.

PPEN127

peripheral protection enable 127

0 (B_0x0): SEC127, PRIV127, and RLOCK127 register bit not present.

1 (B_0x1): SEC127, PRIV127, and RLOCK127 register bit present.

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