stm32 /stm32n6 /STM32N647 /RIFSC /RIFSC_PPSR4

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Interpret as RIFSC_PPSR4

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)PPEN128 0 (B_0x0)PPEN129 0 (B_0x0)PPEN130 0 (B_0x0)PPEN131 0 (B_0x0)PPEN132 0 (B_0x0)PPEN133 0 (B_0x0)PPEN134 0 (B_0x0)PPEN135 0 (B_0x0)PPEN136 0 (B_0x0)PPEN137 0 (B_0x0)PPEN138 0 (B_0x0)PPEN139 0 (B_0x0)PPEN140 0 (B_0x0)PPEN141 0 (B_0x0)PPEN142 0 (B_0x0)PPEN143 0 (B_0x0)PPEN144 0 (B_0x0)PPEN145 0 (B_0x0)PPEN146 0 (B_0x0)PPEN147 0 (B_0x0)PPEN148 0 (B_0x0)PPEN149 0 (B_0x0)PPEN150 0 (B_0x0)PPEN151 0 (B_0x0)PPEN152 0 (B_0x0)PPEN153 0 (B_0x0)PPEN154 0 (B_0x0)PPEN155 0 (B_0x0)PPEN156 0 (B_0x0)PPEN157 0 (B_0x0)PPEN158 0 (B_0x0)PPEN159

PPEN137=B_0x0, PPEN130=B_0x0, PPEN148=B_0x0, PPEN155=B_0x0, PPEN141=B_0x0, PPEN129=B_0x0, PPEN135=B_0x0, PPEN157=B_0x0, PPEN159=B_0x0, PPEN158=B_0x0, PPEN152=B_0x0, PPEN151=B_0x0, PPEN144=B_0x0, PPEN156=B_0x0, PPEN143=B_0x0, PPEN140=B_0x0, PPEN149=B_0x0, PPEN146=B_0x0, PPEN150=B_0x0, PPEN136=B_0x0, PPEN145=B_0x0, PPEN133=B_0x0, PPEN153=B_0x0, PPEN138=B_0x0, PPEN154=B_0x0, PPEN139=B_0x0, PPEN147=B_0x0, PPEN128=B_0x0, PPEN142=B_0x0, PPEN134=B_0x0, PPEN132=B_0x0, PPEN131=B_0x0

Description

RIFSC peripheral protection status register 4

Fields

PPEN128

peripheral protection enable 128

0 (B_0x0): SEC128, PRIV128, and RLOCK128 register bit not present.

1 (B_0x1): SEC128, PRIV128, and RLOCK128 register bit present.

PPEN129

peripheral protection enable 129

0 (B_0x0): SEC129, PRIV129, and RLOCK129 register bit not present.

1 (B_0x1): SEC129, PRIV129, and RLOCK129 register bit present.

PPEN130

peripheral protection enable 130

0 (B_0x0): SEC130, PRIV130, and RLOCK130 register bit not present.

1 (B_0x1): SEC130, PRIV130, and RLOCK130 register bit present.

PPEN131

peripheral protection enable 131

0 (B_0x0): SEC131, PRIV131, and RLOCK131 register bit not present.

1 (B_0x1): SEC131, PRIV131, and RLOCK131 register bit present.

PPEN132

peripheral protection enable 132

0 (B_0x0): SEC132, PRIV132, and RLOCK132 register bit not present.

1 (B_0x1): SEC132, PRIV132, and RLOCK132 register bit present.

PPEN133

peripheral protection enable 133

0 (B_0x0): SEC133, PRIV133, and RLOCK133 register bit not present.

1 (B_0x1): SEC133, PRIV133, and RLOCK133 register bit present.

PPEN134

peripheral protection enable 134

0 (B_0x0): SEC134, PRIV134, and RLOCK134 register bit not present.

1 (B_0x1): SEC134, PRIV134, and RLOCK134 register bit present.

PPEN135

peripheral protection enable 135

0 (B_0x0): SEC135, PRIV135, and RLOCK135 register bit not present.

1 (B_0x1): SEC135, PRIV135, and RLOCK135 register bit present.

PPEN136

peripheral protection enable 136

0 (B_0x0): SEC136, PRIV136, and RLOCK136 register bit not present.

1 (B_0x1): SEC136, PRIV136, and RLOCK136 register bit present.

PPEN137

peripheral protection enable 137

0 (B_0x0): SEC137, PRIV137, and RLOCK137 register bit not present.

1 (B_0x1): SEC137, PRIV137, and RLOCK137 register bit present.

PPEN138

peripheral protection enable 138

0 (B_0x0): SEC138, PRIV138, and RLOCK138 register bit not present.

1 (B_0x1): SEC138, PRIV138, and RLOCK138 register bit present.

PPEN139

peripheral protection enable 139

0 (B_0x0): SEC139, PRIV139, and RLOCK139 register bit not present.

1 (B_0x1): SEC139, PRIV139, and RLOCK139 register bit present.

PPEN140

peripheral protection enable 140

0 (B_0x0): SEC140, PRIV140, and RLOCK140 register bit not present.

1 (B_0x1): SEC140, PRIV140, and RLOCK140 register bit present.

PPEN141

peripheral protection enable 141

0 (B_0x0): SEC141, PRIV141, and RLOCK141 register bit not present.

1 (B_0x1): SEC141, PRIV141, and RLOCK141 register bit present.

PPEN142

peripheral protection enable 142

0 (B_0x0): SEC142, PRIV142, and RLOCK142 register bit not present.

1 (B_0x1): SEC142, PRIV142, and RLOCK142 register bit present.

PPEN143

peripheral protection enable 143

0 (B_0x0): SEC143, PRIV143, and RLOCK143 register bit not present.

1 (B_0x1): SEC143, PRIV143, and RLOCK143 register bit present.

PPEN144

peripheral protection enable 144

0 (B_0x0): SEC144, PRIV144, and RLOCK144 register bit not present.

1 (B_0x1): SEC144, PRIV144, and RLOCK144 register bit present.

PPEN145

peripheral protection enable 145

0 (B_0x0): SEC145, PRIV145, and RLOCK145 register bit not present.

1 (B_0x1): SEC145, PRIV145, and RLOCK145 register bit present.

PPEN146

peripheral protection enable 146

0 (B_0x0): SEC146, PRIV146, and RLOCK146 register bit not present.

1 (B_0x1): SEC146, PRIV146, and RLOCK146 register bit present.

PPEN147

peripheral protection enable 147

0 (B_0x0): SEC147, PRIV147, and RLOCK147 register bit not present.

1 (B_0x1): SEC147, PRIV147, and RLOCK147 register bit present.

PPEN148

peripheral protection enable 148

0 (B_0x0): SEC148, PRIV148, and RLOCK148 register bit not present.

1 (B_0x1): SEC148, PRIV148, and RLOCK148 register bit present.

PPEN149

peripheral protection enable 149

0 (B_0x0): SEC149, PRIV149, and RLOCK149 register bit not present.

1 (B_0x1): SEC149, PRIV149, and RLOCK149 register bit present.

PPEN150

peripheral protection enable 150

0 (B_0x0): SEC150, PRIV150, and RLOCK150 register bit not present.

1 (B_0x1): SEC150, PRIV150, and RLOCK150 register bit present.

PPEN151

peripheral protection enable 151

0 (B_0x0): SEC151, PRIV151, and RLOCK151 register bit not present.

1 (B_0x1): SEC151, PRIV151, and RLOCK151 register bit present.

PPEN152

peripheral protection enable 152

0 (B_0x0): SEC152, PRIV152, and RLOCK152 register bit not present.

1 (B_0x1): SEC152, PRIV152, and RLOCK152 register bit present.

PPEN153

peripheral protection enable 153

0 (B_0x0): SEC153, PRIV153, and RLOCK153 register bit not present.

1 (B_0x1): SEC153, PRIV153, and RLOCK153 register bit present.

PPEN154

peripheral protection enable 154

0 (B_0x0): SEC154, PRIV154, and RLOCK154 register bit not present.

1 (B_0x1): SEC154, PRIV154, and RLOCK154 register bit present.

PPEN155

peripheral protection enable 155

0 (B_0x0): SEC155, PRIV155, and RLOCK155 register bit not present.

1 (B_0x1): SEC155, PRIV155, and RLOCK155 register bit present.

PPEN156

peripheral protection enable 156

0 (B_0x0): SEC156, PRIV156, and RLOCK156 register bit not present.

1 (B_0x1): SEC156, PRIV156, and RLOCK156 register bit present.

PPEN157

peripheral protection enable 157

0 (B_0x0): SEC157, PRIV157, and RLOCK157 register bit not present.

1 (B_0x1): SEC157, PRIV157, and RLOCK157 register bit present.

PPEN158

peripheral protection enable 158

0 (B_0x0): SEC158, PRIV158, and RLOCK158 register bit not present.

1 (B_0x1): SEC158, PRIV158, and RLOCK158 register bit present.

PPEN159

peripheral protection enable 159

0 (B_0x0): SEC159, PRIV159, and RLOCK159 register bit not present.

1 (B_0x1): SEC159, PRIV159, and RLOCK159 register bit present.

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