CPHA=B_0x0, SSOM=B_0x0, MIDI=B_0x0, MASTER=B_0x0, SSOE=B_0x0, CPOL=B_0x0, SSM=B_0x0, AFCNTR=B_0x0, SP=B_0x0, COMM=B_0x0, MSSI=B_0x0, LSBFRST=B_0x0, SSIOP=B_0x0, IOSWP=B_0x0, RDIOM=B_0x0, RDIOP=B_0x0
SPI/I2S configuration register 2
| MSSI | Master SS Idleness 0 (B_0x0): no extra delay 1 (B_0x1): 1 clock cycle period delay added 15 (B_0xF): 15 clock cycle periods delay added |
| MIDI | master Inter-Data Idleness 0 (B_0x0): no delay 1 (B_0x1): 1 clock cycle period delay 15 (B_0xF): 15 clock cycle periods delay |
| RDIOM | RDY signal input/output management 0 (B_0x0): RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect) 1 (B_0x1): RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect) |
| RDIOP | RDY signal input/output polarity 0 (B_0x0): high level of the signal means the slave is ready for communication 1 (B_0x1): low level of the signal means the slave is ready for communication |
| IOSWP | swap functionality of MISO and MOSI pins 0 (B_0x0): no swap 1 (B_0x1): MOSI and MISO are swapped |
| COMM | SPI Communication Mode 0 (B_0x0): full-duplex 1 (B_0x1): simplex transmitter 2 (B_0x2): simplex receiver 3 (B_0x3): half-duplex |
| SP | serial protocol 0 (B_0x0): SPI Motorola 1 (B_0x1): SPI TI |
| MASTER | SPI Master 0 (B_0x0): SPI Slave 1 (B_0x1): SPI Master |
| LSBFRST | data frame format 0 (B_0x0): MSB transmitted first 1 (B_0x1): LSB transmitted first |
| CPHA | clock phase 0 (B_0x0): the first clock transition is the first data capture edge 1 (B_0x1): the second clock transition is the first data capture edge |
| CPOL | clock polarity 0 (B_0x0): SCK signal is at 0 when idle 1 (B_0x1): SCK signal is at 1 when idle |
| SSM | software management of SS signal input 0 (B_0x0): SS input value is determined by the SS PAD 1 (B_0x1): SS input value is determined by the SSI bit |
| SSIOP | SS input/output polarity 0 (B_0x0): low level is active for SS signal 1 (B_0x1): high level is active for SS signal |
| SSOE | SS output enable 0 (B_0x0): SS output is disabled and the SPI can work in multi-master configuration 1 (B_0x1): SS output is enabled. The SPI cannot work in a multi-master environment. It forces the SS pin at inactive level after the transfer is completed or SPI is disabled with respect to SSOM, MIDI, MSSI, SSIOP bits setting |
| SSOM | SS output management in Master mode 0 (B_0x0): SS is kept at active level till data transfer is completed, it becomes inactive with EOT flag 1 (B_0x1): SPI data frames are interleaved with SS non active pulses when MIDI[3:0]>1 |
| AFCNTR | alternate function GPIOs control 0 (B_0x0): The peripheral takes no control of GPIOs while it is disabled 1 (B_0x1): The peripheral keeps always control of all associated GPIOs |