Regviz

stm32 /stm32n6 /STM32N647 /TIM1 /TIM1_DMAR

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Interpret as TIM1_DMAR

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https://regviz.com/r/stm32/stm32h5/STM32H523/TIM1/TIM1_DMAR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DMAB

Description

TIM1 DMA address for full transfer

Fields

DMAB

DMA register for burst accesses

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32