TI1S=B_0x0, ADSYNC=B_0x0, MMS=B_0x0
TIM12 control register 2
| MMS | Master mode selection 0 (B_0x0): Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset. 1 (B_0x1): Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 2 (B_0x2): Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer. 3 (B_0x3): Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo). 4 (B_0x4): Compare - tim_oc1refc signal is used as trigger output (tim_trgo). 5 (B_0x5): Compare - tim_oc2refc signal is used as trigger output (tim_trgo). |
| TI1S | tim_ti1 selection 0 (B_0x0): The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input 1 (B_0x1): The tim_ti1_in[15:0] and tim_ti2_in[15:0] multiplexers output are connected to the tim_ti1 input (XOR combination) |
| ADSYNC | ADC synchronization 0 (B_0x0): The timer operates independently from the ADC 1 (B_0x1): The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 49.4.23 for requirements. |