OPM=B_0x0, ARPE=B_0x0, CEN=B_0x0, DITHEN=B_0x0, UIFREMAP=B_0x0, URS=B_0x0, UDIS=B_0x0
TIM18 control register 1
| CEN | Counter enable 0 (B_0x0): Counter disabled 1 (B_0x1): Counter enabled |
| UDIS | Update disable 0 (B_0x0): UEV enabled. The Update (UEV) event is generated by one of the following events: 1 (B_0x1): UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. |
| URS | Update request source 0 (B_0x0): Any of the following events generates an update interrupt or DMA request if enabled. These events can be: 1 (B_0x1): Only counter overflow/underflow generates an update interrupt or DMA request if enabled. |
| OPM | One-pulse mode 0 (B_0x0): Counter is not stopped at update event 1 (B_0x1): Counter stops counting at the next update event (clearing the CEN bit). |
| ARPE | Auto-reload preload enable 0 (B_0x0): TIMx_ARR register is not buffered. 1 (B_0x1): TIMx_ARR register is buffered. |
| UIFREMAP | UIF status bit remapping 0 (B_0x0): No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1 (B_0x1): Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. |
| DITHEN | Dithering enable 0 (B_0x0): Dithering disabled 1 (B_0x1): Dithering enabled |