TIM5_DCR

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Interpret as TIM5_DCR

DBL=B_0x0, DBA=B_0x0

TIM5 DMA control register

DBA	DMA base address 0 (B_0x0): TIMx_CR1, 1 (B_0x1): TIMx_CR2, 2 (B_0x2): TIMx_SMCR,
DBL	DMA burst length 0 (B_0x0): 1 transfer 1 (B_0x1): 2 transfers 2 (B_0x2): 3 transfers 26 (B_0x1A): 26 transfers
DBSS	DMA burst source selection 1 (B_0x1): Update 2 (B_0x2): CC1 3 (B_0x3): CC2 4 (B_0x4): CC3 5 (B_0x5): CC4 6 (B_0x6): COM 7 (B_0x7): Trigger

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