Regviz

stm32 /stm32n6 /STM32N647 /UCPD /UCPD_CFGR2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as UCPD_CFGR2

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32n6/STM32N645/UCPD/UCPD_CFGR2#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)RXFILTDIS 0 (B_0x0)RXFILT2N3 0 (B_0x0)FORCECLK 0 (B_0x0)WUPEN

FORCECLK=B_0x0, RXFILT2N3=B_0x0, RXFILTDIS=B_0x0, WUPEN=B_0x0

Description

UCPD configuration register 2

Fields

RXFILTDIS

BMC decoder Rx pre-filter enable

0 (B_0x0): Enable

1 (B_0x1): Disable
RXFILT2N3

BMC decoder Rx pre-filter sampling method

0 (B_0x0): 3 samples

1 (B_0x1): 2 samples
FORCECLK

Force ClkReq clock request

0 (B_0x0): Do not force clock request

1 (B_0x1): Force clock request
WUPEN

Wakeup from Stop mode enable

0 (B_0x0): Disable

1 (B_0x1): Enable

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32