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stm32 /stm32n6 /STM32N647 /VENC /VENC_SWREG36

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Interpret as VENC_SWREG36

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SWREG_FIELD

Description

VENC H.264 checkpoint delta QP 1-8/encoder control register 18

Fields

SWREG_FIELD

H.264 Checkpoint delta QP 1-8 / Encoder control register 18 (all format mode)

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32