Regviz

stm32 /stm32n6 /STM32N647 /VENC /VENC_SWREG37

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as VENC_SWREG37

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32n6/STM32N645/VENC/VENC_SWREG37#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SWREG_FIELD

Description

VENC encoder control register 19, stream start offset

Fields

SWREG_FIELD

Encoder control register 19 (all format mode)

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32