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stm32 /stm32n6 /STM32N647 /WWDG /WWDG_CR

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Interpret as WWDG_CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0T0 (B_0x0)WDGA

WDGA=B_0x0

Description

WWDG control register

Fields

T

7-bit counter (MSB to LSB)
WDGA

Activation bit

0 (B_0x0): Watchdog disabled

1 (B_0x1): Watchdog enabled

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32