ABDTR=B_0x0, ADSIZE=B_0x0, DDTR=B_0x0, ABSIZE=B_0x0, ADDTR=B_0x0, DMODE=B_0x0, ADMODE=B_0x0, ISIZE=B_0x0, DQSE=B_0x0, IDTR=B_0x0, IMODE=B_0x0, ABMODE=B_0x0
XSPI communication configuration register
| IMODE | Instruction mode 0 (B_0x0): no instruction 1 (B_0x1): instruction on a single line 2 (B_0x2): instruction on two lines 3 (B_0x3): instruction on four lines 4 (B_0x4): instruction on eight lines |
| IDTR | Instruction double transfer rate 0 (B_0x0): DTR mode disabled for instruction phase 1 (B_0x1): DTR mode enabled for instruction phase |
| ISIZE | Instruction size 0 (B_0x0): 8-bit instruction 1 (B_0x1): 16-bit instruction 2 (B_0x2): 24-bit instruction 3 (B_0x3): 32-bit instruction |
| ADMODE | Address mode 0 (B_0x0): no address 1 (B_0x1): address on a single line 2 (B_0x2): address on two lines 3 (B_0x3): address on four lines 4 (B_0x4): address on eight lines |
| ADDTR | Address double transfer rate 0 (B_0x0): DTR mode disabled for address phase 1 (B_0x1): DTR mode enabled for address phase |
| ADSIZE | Address size 0 (B_0x0): 8-bit address 1 (B_0x1): 16-bit address 2 (B_0x2): 24-bit address 3 (B_0x3): 32-bit address |
| ABMODE | Alternate-byte mode 0 (B_0x0): no alternate bytes 1 (B_0x1): alternate bytes on a single line 2 (B_0x2): alternate bytes on two lines 3 (B_0x3): alternate bytes on four lines |
| ABDTR | Alternate bytes double transfer rate 0 (B_0x0): DTR mode disabled for alternate bytes phase 1 (B_0x1): DTR mode enabled for alternate bytes phase |
| ABSIZE | Alternate bytes size 0 (B_0x0): 8-bit alternate bytes 1 (B_0x1): 16-bit alternate bytes 2 (B_0x2): 24-bit alternate bytes 3 (B_0x3): 32-bit alternate bytes |
| DMODE | Data mode 0 (B_0x0): no data 1 (B_0x1): data on a single line 2 (B_0x2): data on two lines 3 (B_0x3): data on four lines 4 (B_0x4): data on eight lines 5 (B_0x5): data on 16 lines |
| DDTR | Data double transfer rate 0 (B_0x0): DTR mode disabled for data phase 1 (B_0x1): DTR mode enabled for data phase |
| DQSE | DQS enable 0 (B_0x0): DQS disabled 1 (B_0x1): DQS enabled |