EN=B_0x0, DMAEN=B_0x0, NOPREF_AXI=B_0x0, PMM=B_0x0, APMS=B_0x0, TCIE=B_0x0, FTHRES=B_0x0, TEIE=B_0x0, ABORT=B_0x0, TOIE=B_0x0, SMIE=B_0x0, DMM=B_0x0, FTIE=B_0x0, NOPREF=B_0x0, CSSEL=B_0x0, MSEL=B_0x0, FMODE=B_0x0, TCEN=B_0x0
XSPI control register
| EN | Enable 0 (B_0x0): XSPI disabled 1 (B_0x1): XSPI enabled |
| ABORT | Abort request 0 (B_0x0): no abort requested 1 (B_0x1): abort requested |
| DMAEN | DMA enable 0 (B_0x0): DMA disabled for indirect mode 1 (B_0x1): DMA enabled for indirect mode |
| TCEN | Timeout counter enable 0 (B_0x0): timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely after an access in memory-mapped mode. 1 (B_0x1): timeout counter is enabled, and thus the chip-select is released in the memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity. |
| DMM | Dual-memory configuration 0 (B_0x0): dual-memory configuration disabled 1 (B_0x1): dual-memory configuration enabled |
| FTHRES | FIFO threshold level 0 (B_0x0): FTF is set if there are one or more free bytes available to be written to in the FIFO in indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in indirect-read mode. 1 (B_0x1): FTF is set if there are two or more free bytes available to be written to in the FIFO in indirect-write mode, or if there are two or more valid bytes can be read from the FIFO in indirect-read mode. 63 (B_0x3F): FTF is set if there are 64 free bytes available to be written to in the FIFO in indirect-write mode, or if there are 64 valid bytes can be read from the FIFO in indirect-read mode. |
| TEIE | Transfer error interrupt enable 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled |
| TCIE | Transfer complete interrupt enable 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled |
| FTIE | FIFO threshold interrupt enable 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled |
| SMIE | Status match interrupt enable 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled |
| TOIE | Timeout interrupt enable 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled |
| APMS | Automatic status-polling mode stop 0 (B_0x0): Automatic status-polling mode is stopped only by abort or by disabling the XSPI. 1 (B_0x1): Automatic status-polling mode stops as soon as there is a match. |
| PMM | Polling match mode 0 (B_0x0): AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register. 1 (B_0x1): OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register. |
| CSSEL | chip select selection 0 (B_0x0): NCS1 active 1 (B_0x1): NCS2 active |
| NOPREF | no prefetch data 0 (B_0x0): automatic prefetch enabled 1 (B_0x1): automatic prefetch disabled |
| NOPREF_AXI | no prefetch for signaled AXI transactions 0 (B_0x0): prefetch is enabled for AXI signaled transactions. 1 (B_0x1): prefetch is disable for AXI signaled transactions. |
| FMODE | Functional mode 0 (B_0x0): indirect-write mode 1 (B_0x1): indirect-read mode 2 (B_0x2): automatic status-polling mode 3 (B_0x3): memory-mapped mode |
| MSEL | Flash select 0 (B_0x0): data exchanged over IO[3:0] 1 (B_0x1): data exchanged over IO[7:4] 2 (B_0x2): data exchanged over IO[11:8] 3 (B_0x3): data exchanged over IO[15:12] |