stm32 /stm32n6 /STM32N647 /XSPI1 /XSPI_HLCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as XSPI_HLCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LM 0 (B_0x0)WZL 0TACC0TRWR

WZL=B_0x0, LM=B_0x0

Description

XSPI HyperBus latency configuration register

Fields

LM

Latency mode

0 (B_0x0): Variable initial latency

1 (B_0x1): Fixed latency

WZL

Write zero latency

0 (B_0x0): latency on write accesses

1 (B_0x1): no latency on write accesses

TACC

None

TRWR

Read write recovery time

Links

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