VBATEN=B_0x0, DUAL=B_0x0, VREFEN=B_0x0, DAMDF=B_0x0
ADC12 common control register
| DUAL | Dual ADC mode selection 0 (B_0x0): Independent mode 1 (B_0x1): Combined regular simultaneous + Injected simultaneous mode 2 (B_0x2): Combined regular simultaneous + Alternate trigger mode 3 (B_0x3): Combined Interleaved mode + Injected simultaneous mode 5 (B_0x5): Injected simultaneous mode only 6 (B_0x6): Regular simultaneous mode only 7 (B_0x7): Interleaved mode only 9 (B_0x9): Alternate trigger mode only |
| DELAY | Delay between two sampling phases |
| DAMDF | Dual ADC mode data format 0 (B_0x0): Dual ADC mode without data packing (ADCx_CDR and ADCx_CDR2 registers not used). 2 (B_0x2): Data formatting mode for any data width (ADCx_CDR data register is used when the data width is less than 16 bits, otherwise ADCx_CDR2 register is used) 3 (B_0x3): Data formatting mode for data width lower that 8 bits (ADCx_CDR data register is used) |
| VREFEN | Vless thansub>REFINTless than/sub> enable 0 (B_0x0): Vless thansub>REFINTless than/sub> channel disabled 1 (B_0x1): Vless thansub>REFINTless than/sub> channel enabled |
| VBATEN | VBAT enable 0 (B_0x0): Vless thansub>BATless than/sub> channel disabled 1 (B_0x1): Vless thansub>BATless than/sub> channel enabled |