ADC12 common status register
| ADRDY_MST | Master ADC ready |
| EOSMP_MST | End of Sampling phase flag of the master ADC |
| EOC_MST | End of regular conversion of the master ADC |
| EOS_MST | End of regular sequence flag of the master ADC |
| OVR_MST | Overrun flag of the master ADC |
| JEOC_MST | End of injected conversion flag of the master ADC |
| JEOS_MST | End of injected sequence flag of the master ADC |
| AWD1_MST | Analog watchdog 1 flag of the master ADC |
| AWD2_MST | Analog watchdog 2 flag of the master ADC |
| AWD3_MST | Analog watchdog 3 flag of the master ADC |
| ADRDY_SLV | Slave ADC ready |
| EOSMP_SLV | End of Sampling phase flag of the slave ADC |
| EOC_SLV | End of regular conversion of the slave ADC |
| EOS_SLV | End of regular sequence flag of the slave ADC. This bit is a copy of the EOS bit in the corresponding ADC_ISR register. |
| OVR_SLV | Overrun flag of the slave ADC |
| JEOC_SLV | End of injected conversion flag of the slave ADC |
| JEOS_SLV | End of injected sequence flag of the slave ADC |
| AWD1_SLV | Analog watchdog 1 flag of the slave ADC |
| AWD2_SLV | Analog watchdog 2 flag of the slave ADC |
| AWD3_SLV | Analog watchdog 3 flag of the slave ADC |