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stm32 /stm32n6 /STM32N655 /CSI /CSI_FCR1

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Interpret as CSI_FCR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CESOTDL0F)CESOTDL0F 0 (CESOTSYNCDL0F)CESOTSYNCDL0F 0 (CEESCDL0F)CEESCDL0F 0 (CESYNCESCDL0F)CESYNCESCDL0F 0 (CECTRLDL0F)CECTRLDL0F 0 (CESOTDL1F)CESOTDL1F 0 (CESOTSYNCDL1F)CESOTSYNCDL1F 0 (CEESCDL1F)CEESCDL1F 0 (CESYNCESCDL1F)CESYNCESCDL1F 0 (CECTRLDL1F)CECTRLDL1F

Description

CSI-2 Host flag clear register 1

Fields

CESOTDL0F

Clear SOT error flag on lane 0
CESOTSYNCDL0F

Clear SOT synchronization error flag on lane 0
CEESCDL0F

Clear D-PHY_RX lane 0 escape entry error flag
CESYNCESCDL0F

Clear D-PHY_RX lane 0 low-power data transmission synchronization error flag
CECTRLDL0F

Clear D-PHY_RX lane 0 control error flag
CESOTDL1F

Clear SOT error flag on lane 1
CESOTSYNCDL1F

Clear SOT synchronization error flag on lane 1
CEESCDL1F

Clear D-PHY_RX lane 1 escape entry error flag
CESYNCESCDL1F

Clear D-PHY_RX lane 1 low-power data transmission synchronization error flag
CECTRLDL1F

Clear D-PHY_RX lane 1 control error flag

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32