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stm32 /stm32n6 /STM32N655 /CSI /CSI_IER1

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Interpret as CSI_IER1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)ESOTDL0IE 0 (B_0x0)ESOTSYNCDL0IE 0 (B_0x0)EESCDL0IE 0 (B_0x0)ESYNCESCDL0IE 0 (B_0x0)ECTRLDL0IE 0 (B_0x0)ESOTDL1IE 0 (B_0x0)ESOTSYNCDL1IE 0 (B_0x0)EESCDL1IE 0 (B_0x0)ESYNCESCDL1IE 0 (B_0x0)ECTRLDL1IE

EESCDL0IE=B_0x0, ECTRLDL0IE=B_0x0, ESOTSYNCDL0IE=B_0x0, ESOTDL0IE=B_0x0, ESOTDL1IE=B_0x0, EESCDL1IE=B_0x0, ECTRLDL1IE=B_0x0, ESOTSYNCDL1IE=B_0x0, ESYNCESCDL0IE=B_0x0, ESYNCESCDL1IE=B_0x0

Description

CSI-2 Host interrupt enable register 1

Fields

ESOTDL0IE

SOT error interrupt enable on lane 0

0 (B_0x0): Lane 0 SOT interrupt error disabled

1 (B_0x1): Lane 0 SOT interrupt error enabled
ESOTSYNCDL0IE

SOT synchronization interrupt error enable on lane 0

0 (B_0x0): Lane 0 SOT synchronization interrupt error disabled

1 (B_0x1): Lane 0 SOT synchronization interrupt error enabled
EESCDL0IE

D-PHY_RX lane 0 escape entry error interrupt enable

0 (B_0x0): Lane 0 unrecognized escape entry command interrupt error disabled

1 (B_0x1): Lane 0 unrecognized escape entry command interrupt error enabled
ESYNCESCDL0IE

D-PHY_RX lane 0 low power data transmission synchronization error interrupt enable

0 (B_0x0): Lane 0 low-power data transmission interrupt error disabled

1 (B_0x1): Lane 0 low-power data transmission Interrupt error enabled
ECTRLDL0IE

D-PHY_RX lane 0 control error interrupt enable

0 (B_0x0): Lane 0 control error interrupt disabled

1 (B_0x1): Lane 0 control error interrupt enabled
ESOTDL1IE

SOT error interrupt enable on lane 1

0 (B_0x0): Lane 1 SOT interrupt error disabled

1 (B_0x1): Lane 1 SOT interrupt error enabled
ESOTSYNCDL1IE

SOT synchronization interrupt error enable on lane 1

0 (B_0x0): Lane 1 SOT synchronization interrupt error disabled

1 (B_0x1): Lane 1 SOT synchronization interrupt error enabled
EESCDL1IE

D-PHY_RX lane 1 escape entry error interrupt enable

0 (B_0x0): Lane 1 unrecognized escape entry command interrupt error disabled

1 (B_0x1): Lane 1 unrecognized escape entry command interrupt error enabled
ESYNCESCDL1IE

D-PHY_RX lane 1 low-power data transmission synchronization error interrupt enable

0 (B_0x0): Lane 1 low-power data transmission interrupt error disabled

1 (B_0x1): Lane 1 low-power data transmission Interrupt error enabled
ECTRLDL1IE

D-PHY_RX lane 1 control error interrupt enable

0 (B_0x0): Lane 1 control error interrupt disabled

1 (B_0x1): Lane 1 control error interrupt enabled

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32