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stm32 /stm32n6 /STM32N655 /CSI /CSI_PFCR

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Interpret as CSI_PFCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CCFR0HSFR0 (B_0x0)DLD

DLD=B_0x0

Description

CSI PHY frequency control register

Fields

CCFR

Configuration clock frequency range selection
HSFR

PHY high-speed frequency range selection
DLD

Data lane direction of lane 0

0 (B_0x0): Rx

1 (B_0x1): Tx

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32