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stm32 /stm32n6 /STM32N655 /CSI /CSI_PTCR0

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Interpret as CSI_PTCR0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TCKEN)TCKEN 0 (TRSEN)TRSEN

Description

CSI PHY test control register 0

Fields

TCKEN

Test-interface clock enable for the TDI bus into the PHY
TRSEN

Test-interface reset enable for the TDI bus into the PHY

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32