CSI-2 Host status register 1
| ESOTDL0F | SOT error flag on lane 0 |
| ESOTSYNCDL0F | SOT synchronization error flag on lane 0 |
| EESCDL0F | D-PHY_RX lane 0 escape entry error flag |
| ESYNCESCDL0F | D-PHY_RX lane 0 low-power data transmission synchronization error flag |
| ECTRLDL0F | D-PHY_RX lane 0 control error flag |
| ESOTDL1F | SOT error flag on lane 1 |
| ESOTSYNCDL1F | SOT synchronization error flag on lane 1 |
| EESCDL1F | D-PHY_RX lane 1 escape entry error flag |
| ESYNCESCDL1F | D-PHY_RX lane 1 low-power data transmission synchronization error flag |
| ECTRLDL1F | D-PHY_RX lane 1 control error flag |
| ACTDL0F | D-PHY_RX lane 0 high-speed reception active |
| SYNCDL0F | D-PHY_RX lane 0 receiver synchronization observed |
| SKCALDL0F | D-PHY_RX lane 0 high-speed skew calibration |
| STOPDL0F | D-PHY_RX receiver data lane 0 in stop state |
| ULPNDL0F | D-PHY_RX receiver ultra-low-power state (not) active on data lane 0 |
| ACTDL1F | D-PHY_RX lane 1 high-speed reception active |
| SYNCDL1F | D-PHY_RX lane 1 receiver synchronization observed |
| SKCALDL1F | D-PHY_RX lane 1 high-speed skew calibration |
| STOPDL1F | D-PHY_RX receiver data lane 1 in stop state |
| ULPNDL1F | D-PHY_RX receiver ultra-low-power state (not) active on data lane 1 |
| STOPCLF | D-PHY_RX receiver in stop state for the clock lane |
| ULPNACTF | D-PHY_RX receiver ULP state (not) active |
| ULPNCLF | D-PHY_RX receiver Ultra-Low power state (not) on clock lane. |
| ACTCLF | D-PHY_RX receiver clock active flag |