P2CPTACT=B_0x0, P1CPTACT=B_0x0, P0CPTACT=B_0x0, PRVSYNC=B_0x0, PRHSYNC=B_0x0
DCMIPP common status register 1
| PRHSYNC | This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel interface if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in HPOL bit of the DCMIPP_PRCR register, and cleared otherwise. 0 (B_0x0): Active line 1 (B_0x1): Synchronization between lines |
| PRVSYNC | This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel interface if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in VPOL bit of the DCMIPP_PRCR register, and cleared otherwise. 0 (B_0x0): Active frame 1 (B_0x1): Synchronization between frames |
| P0LSTLINE | Last line LSB bit, sampled at Frame capture complete event for Pipe0 |
| P0LSTFRM | Last frame LSB bit, sampled at Frame capture complete event for Pipe0 |
| P0CPTACT | Active frame capture (active from start-of-frame to frame complete) for Pipe0 0 (B_0x0): No capture currently active 1 (B_0x1): Capture currently active |
| P1LSTLINE | Last line LSB bit, sampled at Frame capture complete event for Pipe1 |
| P1LSTFRM | Last frame LSB bit, sampled at frame capture complete event for Pipe1 |
| P1CPTACT | Active frame capture (active from start-of-frame to frame complete) for Pipe1 0 (B_0x0): No capture currently active 1 (B_0x1): Capture currently active |
| P2LSTLINE | Last line LSB bit, sampled at frame capture complete event for Pipe2 |
| P2LSTFRM | Last frame LSB bit, sampled at frame capture complete event for Pipe2 |
| P2CPTACT | Active frame capture (active from start-of-frame to frame complete) for Pipe2 0 (B_0x0): No capture currently active 1 (B_0x1): Capture currently active |