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stm32 /stm32n6 /STM32N655 /DCMIPP /DCMIPP_P1CDCCR

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Interpret as DCMIPP_P1CDCCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)ENABLE 0 (B_0x0)HDEC 0 (B_0x0)VDEC

HDEC=B_0x0, ENABLE=B_0x0, VDEC=B_0x0

Description

DCMIPP Pipex current decimation register

Fields

ENABLE

None

0 (B_0x0): Bypass: decimation is not active, all pixels are transmitted

1 (B_0x1): Enable: one pixel every 1, 2, 4 or 8, in H and V is transmitted, following HDEC and VDEC
HDEC

Horizontal decimation ratio

0 (B_0x0): All pixels are transmitted, no horizontal decimation

1 (B_0x1): One line out of two transmitted
VDEC

Vertical decimation ratio

0 (B_0x0): All pixels are transmitted, no vertical decimation

1 (B_0x1): One line out of two transmitted

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32