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stm32 /stm32n6 /STM32N655 /DCMIPP /DCMIPP_P1CMRICR

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Interpret as DCMIPP_P1CMRICR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)ROILSZ 0 (B_0x0)ROI1EN 0 (B_0x0)ROI2EN 0 (B_0x0)ROI3EN 0 (B_0x0)ROI4EN 0 (B_0x0)ROI5EN 0 (B_0x0)ROI6EN 0 (B_0x0)ROI7EN 0 (B_0x0)ROI8EN

ROI5EN=B_0x0, ROI1EN=B_0x0, ROILSZ=B_0x0, ROI3EN=B_0x0, ROI6EN=B_0x0, ROI8EN=B_0x0, ROI7EN=B_0x0, ROI2EN=B_0x0, ROI4EN=B_0x0

Description

DCMIPP Pipex common ROI configuration register

Fields

ROILSZ

Region of interest line size width

0 (B_0x0): Line width 1 pixel

1 (B_0x1): Line width 2 pixels

2 (B_0x2): Line width 4 pixels

3 (B_0x3): Line width 8 pixels
ROI1EN

Region of interest 1 enable

0 (B_0x0): Disable ROI

1 (B_0x1): Enable ROI
ROI2EN

Region of interest 2 enable

0 (B_0x0): Disable ROI

1 (B_0x1): Enable ROI
ROI3EN

Region of interest 3 enable

0 (B_0x0): Disable ROI

1 (B_0x1): Enable ROI
ROI4EN

Region of interest 4 enable

0 (B_0x0): Disable ROI

1 (B_0x1): Enable ROI
ROI5EN

Region of interest 5 enable

0 (B_0x0): Disable ROI

1 (B_0x1): Enable ROI
ROI6EN

Region of interest 6 enable

0 (B_0x0): Disable ROI

1 (B_0x1): Enable ROI
ROI7EN

Region of interest 7 enable

0 (B_0x0): Disable ROI

1 (B_0x1): Enable ROI
ROI8EN

Region of interest 8 enable

0 (B_0x0): Disable ROI

1 (B_0x1): Enable ROI

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32